The present invention generally relates to a packaging technique for integrated circuit device, and more particularly to a flip chip bonding leadframe-type packaging method for integrated circuit device and an integrated circuit device formed by the packaging method.
In the trend of increasing density and working frequency and decreasing working voltage of integrated circuit devices, many bottlenecks exist in circuit design for placing more functions in limited chip area and meeting the requirements for faster execution speed and less interference. The bottlenecks exist because the ever decreasing line width and line pitch of the integrated circuit lead to greater interference and internal resistance that not only slows down the speed of signal transmission but also affects the completeness of the signals. Therefore, with respect to high speed integrated circuit device, under the circumstance where the internal resistance of the device cannot be reduced to increase the speed of the signal transmission, it is an inevitable trend of the electronic products to reduce the inductance of the package itself through an improved packaging technique and thus enhance the execution speed of the entire device.
The packaging technique of the integrated circuit mainly relates to the chip carrier and the electrical connection between the chip and the chip carrier. With respect to the chip carrying manners, they can be substantially divided into two types: leadframe and organic or ceramic base board. In the former, the long transmission distance between the inner lead fingers and outer lead fingers of the leadframe will create great inductance, which will lower the execution speed of the entire device. However, the manufacturing cost for such chip carrier is relatively low. In the latter, tin balls are used instead of the outer lead fingers of the leadframe so that the transmission distance is greatly shortened, which reduces the inductance of the package itself and thus increase the execution speed of the entire device. However, the manufacturing cost for such chip carrier is relatively high, especially in comparison with the manufacturing cost for the leadframe with low finger number. In addition, in terms of the electric connection between the chip and the chip carrier, there are generally three types of connection: wire bonding, tape automatic bonding and flip chip bonding. In the three types of electric connection, the flip chip bonding has shortest signal transmission distance so that the inductance of the transmission line thereof is least and the transmission speed thereof is fastest. In the products of the organic base board or ceramic base board type chip carriers, the electric connection measures include the above three types of bonding. However, with respect to the leadframe-type chip carrier, most of the electric connection measures employ wire bonding and only few adopt tape automatic bonding for electric connection, for example, in U.S. Pat. No. 5,252,853 as shown in FIGS. 1 and 2. It has not seen that flip chip bonding be used as the electric connection measure. In FIG. 1, the integrated circuit chip 1 has multiple ground pads 2, power pads 3 and signal pads 4. Also, the chip 1 is disposed with a polyimide film 5 for blocking .alpha. ray. The tape 10 is composed of a polyimide tape 9, ground lead 6, power lead 7 and signal leads 8. These leads are fixedly located on the polyimide tape 9, permitting the internal terminals of the leads to be directly connected with the related solder pads of the chip. FIG. 2 is a sectional view taken along line A--A of FIG. 1.
The reason that the leadframe-type chip carrier does not employ flip chip bonding as the electric connection mainly resides in that the products to which the flip chip bonding technique is applied generally have more input/output (I/O) numbers. In the case that leadframe is used as the chip carrier, the I/O must be arranged by rows rather than a matrix. Accordingly, not only the difficulty in assembly of the chip with the leadframe is increased, but also the difficulty of manufacture of the leadframe with fine pitch. In addition, the biggest problem is how to form solder-attachable top surface metallurgy (referred to as TSM hereinafter) on the leadframe, enabling the solder bumps of the chip to be fused with the leadframe and how to keep the coplanarity of the respective lead fingers of the leadframe to avoid false soldering during assembly of the chip with the lead fingers of the leadframe.
Conventionally, the lead fingers of the leadframe are sprayed with an electroplating liquid to form a metal layer for facilitating fusion of gold wires with the lead fingers during connection operation. With such metal layer in electroplating measure, the electroplating area can be hardly very small so that the range of the electroplating metal on the lead fingers will spread to and bridge two sides of the internal lead fingers. In the case that the solder bumps of the flip chip are fused with the lead fingers of the leadframe, due to the excessively large area of the TSM on the lead fingers, the molten solder will spread around. This will result in uncontrollable fusion height of the solder bumps and the lead fingers or failure of fusion. Also, in the conventional leadframe manufacturing, no matter whether an etching or a punching measure is used, the coplanarity of the lead fingers can be hardly controlled to be under 4 mils. As a result, in assembling, in the case that the height of the solder bumps is too low, false soldering may take place to lead to failure of assembly.